1. Field of the Invention
The present invention relates to a non-volatile memory device and fabricating method thereof, and more particularly, to a non-volatile memory device having a high coupling ratio and fabricating method thereof.
2. Discussion of the Related Art
Generally, semiconductor memory devices are categorized into a volatile memory device, which loses data in case of cutting off power supply, such as DRAM (dynamic random access memory) and SRAM (static random access memory) and a non-volatile memory device, which saves data in spite of cutting off power supply, such as a flash memory device.
FIG. 1 is a cross-sectional diagram of a non-volatile memory device according to a related art.
Referring to FIG. 1, a tunnel oxide layer pattern 106 and a floating gate conductor layer pattern 108 are sequentially stacked on an active area 104 of a semiconductor substrate 100 defined by a device isolation layer 102.
A gate-to-gate insulating layer 110 is formed on the floating gate conductor layer pattern 108 and the device isolation layer 102. The gate-to-gate insulating layer 110 consists of an oxide/nitride/oxide (ONO) layer.
And, a control gate conductor layer 112 is arranged on the gate-to-gate insulating layer 110.
In operating the above-configured non-volatile memory device, a ratio of voltage coupled to the floating gate conductor layer pattern 108 by a voltage applied to the control gate conductor layer 112 is called a coupling ratio. And, it is well known that the speed and performance of the device are enhanced by high coupling ratio. The coupling ratio can be expressed by Equation 1.
                    γ        =                              C            ONO                                              C              ONO                        +                          C              tunnel                                                          [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, CONO is capacitance between the floating gate conductor layer pattern 108 and the control gate conductor layer patter 112 and Ctunnel is capacitance between the floating gate conductor layer pattern 108 and a bulk, i.e., channel.
As can be known by Equation 1, CONO should be increased to raise the coupling ratio. For this, a contact area between the floating gate conductor layer pattern 108 and the gate-to-gate insulating layer 110 needs to be increased.
However, if a width of the active area is increased to increase the contact area between the floating gate conductor layer pattern 108 and the gate-to-gate insulating layer 110, the degree of device integration is lowered.
In case a height of the floating gate conductor layer pattern 108 is raised, it is difficult to carryout an etch process thereof.